• High-speed Multiplier Design Using Multi-Operand Multipliers

      Nezhad, Mohammad Reza Reshadi; Navi, Kaivan; Department of Electrical and Computer engineering, Shahid Beheshti University, G.C., Tehran, Tehran 1983963113, Iran; Faculty of Department of Computer engineering, University of Isfahan, Isfahan, Isfahan 8174673440, Iran (IJCSN, 2012-04-01)
      Multiplication is one of the major bottlenecks in most digital computing and signal processing systems, which depends on the word size to be executed. This paper presents three deferent designs for three-operand 4-bit multiplier for positive integer multiplication, and compares them in regard to timing, dynamic power, and area with classical method of multiplication performed on today architects. The three-operand 4-bit multipliers structure introduced, serves as a building block for three-operand multipliers in general