A SOFT-COMPUTING BASED SYSTEM LEVEL DESIGN SPACE EXPLORATION METHODOLOGY FOR SYSTEM-ON-CHIP DESIGNS
dc.contributor.advisor | Rozenblit, Jerzy W. | en_US |
dc.contributor.author | Wu, Qinglong | |
dc.creator | Wu, Qinglong | en_US |
dc.date.accessioned | 2011-10-19T20:15:51Z | |
dc.date.available | 2011-10-19T20:15:51Z | |
dc.date.issued | 2009 | |
dc.identifier.uri | http://hdl.handle.net/10150/146065 | |
dc.description.abstract | This dissertation presents a novel intelligent embedded multi-objective multiple design space exploration methodology (IMODE) to support fast early system level System-on-Chip (SoC) design space exploration in order to improve design productivity and quality. The IMODE methodology uses two soft-computing technologies - a Pareto multi-objective genetic algorithm and a fuzzy logic system at their respective advantages to effectively and efficiently explore multiple large design spaces and make intelligent design decisions. The design space search process is guided by the Pareto multi-objective genetic algorithm to heuristically cover large design spaces and the design decision is performed by the fuzzy logic system based decision making engine which introduces another layer of computation intelligence on top of the intelligent design space search process. The IMODE methodology is unique and more comprehensive than many other existing SoC design space exploration methodologies in that design space exploration and decision making are two separated but still interdependent processes, and all heterogeneous design space explorations - computation/core exploration, communication architecture exploration, and physical design exploration, are integrated into a single SoC exploration flow and covered with a unified methodology which can significantly improve methodology continuity. | |
dc.language.iso | en | en_US |
dc.publisher | The University of Arizona. | en_US |
dc.rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | en_US |
dc.title | A SOFT-COMPUTING BASED SYSTEM LEVEL DESIGN SPACE EXPLORATION METHODOLOGY FOR SYSTEM-ON-CHIP DESIGNS | en_US |
dc.type | text | en_US |
dc.type | Electronic Dissertation | en_US |
dc.identifier.oclc | 659753607 | |
thesis.degree.grantor | University of Arizona | en_US |
thesis.degree.level | doctoral | en_US |
dc.contributor.committeemember | Akoglu, Ali | en_US |
dc.contributor.committeemember | Lysecky, Roman | en_US |
dc.description.release | Embargo: Release after 12/2/2011 | en_US |
dc.identifier.proquest | 10767 | |
thesis.degree.discipline | Graduate College | en_US |
thesis.degree.discipline | Electrical & Computer Engineering | en_US |
thesis.degree.name | Ph.D. | en_US |
refterms.dateFOA | 2018-06-15T21:32:25Z | |
html.description.abstract | This dissertation presents a novel intelligent embedded multi-objective multiple design space exploration methodology (IMODE) to support fast early system level System-on-Chip (SoC) design space exploration in order to improve design productivity and quality. The IMODE methodology uses two soft-computing technologies - a Pareto multi-objective genetic algorithm and a fuzzy logic system at their respective advantages to effectively and efficiently explore multiple large design spaces and make intelligent design decisions. The design space search process is guided by the Pareto multi-objective genetic algorithm to heuristically cover large design spaces and the design decision is performed by the fuzzy logic system based decision making engine which introduces another layer of computation intelligence on top of the intelligent design space search process. The IMODE methodology is unique and more comprehensive than many other existing SoC design space exploration methodologies in that design space exploration and decision making are two separated but still interdependent processes, and all heterogeneous design space explorations - computation/core exploration, communication architecture exploration, and physical design exploration, are integrated into a single SoC exploration flow and covered with a unified methodology which can significantly improve methodology continuity. |