Sequential circuits fault simulation using fan out stem based techniques.

Abstract

This dissertation describes a new simulation technique for an automatic test generation system, SCIRTSS version 4.0 (Sequential Circuit Test Sequence System). This test generation system is driven by the hardware compiler AHPL, a Hardware Programming Language, and an intelligent heuristic-based search for test vector generation. Using a fault-injection gate-level simulator and the generated test vector, all the faulty states of the circuit are simulated in parallel and the simulator is thus able to find all detected faults by a particular input sequence. The major objective of this research was to develop a faster replacement for the existing simulation process. The philosophy of divide and conquer is used in the development of the new simulation technique. Sequential networks are divided into combinational sub-networks, and, if necessary, the combinational sub-networks are further reduced into fan-out free regions. Thus, the problem is reduced to a relatively simple combinational one. In addition to the classical faults, the new simulator attempts to detect CMOS stuck-open faults. Several circuits were tested under SCIRTSS 4.0 using both the existing and the new simulation techniques. The results are listed in this paper to verify superiority of the new simulation technique.