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dc.contributor.authorAbuelyaman, Eltayeb Salih.
dc.creatorAbuelyaman, Eltayeb Salih.en_US
dc.date.accessioned2011-10-31T17:09:05Z
dc.date.available2011-10-31T17:09:05Z
dc.date.issued1988en_US
dc.identifier.urihttp://hdl.handle.net/10150/184466
dc.description.abstractThis dissertation describes a new simulation technique for an automatic test generation system, SCIRTSS version 4.0 (Sequential Circuit Test Sequence System). This test generation system is driven by the hardware compiler AHPL, a Hardware Programming Language, and an intelligent heuristic-based search for test vector generation. Using a fault-injection gate-level simulator and the generated test vector, all the faulty states of the circuit are simulated in parallel and the simulator is thus able to find all detected faults by a particular input sequence. The major objective of this research was to develop a faster replacement for the existing simulation process. The philosophy of divide and conquer is used in the development of the new simulation technique. Sequential networks are divided into combinational sub-networks, and, if necessary, the combinational sub-networks are further reduced into fan-out free regions. Thus, the problem is reduced to a relatively simple combinational one. In addition to the classical faults, the new simulator attempts to detect CMOS stuck-open faults. Several circuits were tested under SCIRTSS 4.0 using both the existing and the new simulation techniques. The results are listed in this paper to verify superiority of the new simulation technique.
dc.language.isoenen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectIntegrated circuits -- Defects.en_US
dc.subjectIntegrated circuits -- Testing.en_US
dc.subjectComputer simulation.en_US
dc.titleSequential circuits fault simulation using fan out stem based techniques.en_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.identifier.oclc701356443en_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.leveldoctoralen_US
dc.identifier.proquest8824260en_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.namePh.D.en_US
refterms.dateFOA2018-08-22T18:44:46Z
html.description.abstractThis dissertation describes a new simulation technique for an automatic test generation system, SCIRTSS version 4.0 (Sequential Circuit Test Sequence System). This test generation system is driven by the hardware compiler AHPL, a Hardware Programming Language, and an intelligent heuristic-based search for test vector generation. Using a fault-injection gate-level simulator and the generated test vector, all the faulty states of the circuit are simulated in parallel and the simulator is thus able to find all detected faults by a particular input sequence. The major objective of this research was to develop a faster replacement for the existing simulation process. The philosophy of divide and conquer is used in the development of the new simulation technique. Sequential networks are divided into combinational sub-networks, and, if necessary, the combinational sub-networks are further reduced into fan-out free regions. Thus, the problem is reduced to a relatively simple combinational one. In addition to the classical faults, the new simulator attempts to detect CMOS stuck-open faults. Several circuits were tested under SCIRTSS 4.0 using both the existing and the new simulation techniques. The results are listed in this paper to verify superiority of the new simulation technique.


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