A computer-aided design framework for modeling and simulation of VLSI interconnects.
dc.contributor.author | Hsu, Pochang. | |
dc.creator | Hsu, Pochang. | en_US |
dc.date.accessioned | 2011-10-31T18:06:52Z | |
dc.date.available | 2011-10-31T18:06:52Z | |
dc.date.issued | 1993 | en_US |
dc.identifier.uri | http://hdl.handle.net/10150/186363 | |
dc.description.abstract | The rising complexity of interconnect and packaging structures in VLSI systems has increased the necessity of applying modeling and simulation techniques for analysis and design. To effectively manage design data and CAD tools for modeling and simulations of electronic packaging, a framework which provides different levels of services is essential. This paper discusses a computer-aided design framework for the aforementioned purposes. A CAD framework with a five layered architecture is developed to support the analysis and design for VLSI packaging and interconnects. The first layer of the framework emphasizes the fundamental integration of CAD tools and simulation management. In the second layer of the architecture, design data representation and management are stressed. Two design databases termed the Chip Model Library and the Packaging Model Library are developed and coupled in this layer. We applied an object-oriented approach to implement libraries and encapsulate CAD tools. System level (board level) modeling and simulation are presented in the third layer of the framework. CMOS based multichip modules (MCMs) are used for our discussion. The fourth layer is for the automation of design process by coordinating different CAD tools. The highest layer in the proposed CAD framework is the level for design methodology management. A rule and frame based system is illustrated for simulation model generation of electronic packages. | |
dc.language.iso | en | en_US |
dc.publisher | The University of Arizona. | en_US |
dc.rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | en_US |
dc.subject | Dissertations, Academic. | en_US |
dc.subject | Electrical engineering. | en_US |
dc.title | A computer-aided design framework for modeling and simulation of VLSI interconnects. | en_US |
dc.type | text | en_US |
dc.type | Dissertation-Reproduction (electronic) | en_US |
dc.contributor.chair | Rozenblit, Jerzy W. | en_US |
dc.identifier.oclc | 720402560 | en_US |
thesis.degree.grantor | University of Arizona | en_US |
thesis.degree.level | doctoral | en_US |
dc.contributor.committeemember | Prince, John L. | en_US |
dc.contributor.committeemember | Hill, Frederick J. | en_US |
dc.identifier.proquest | 9408395 | en_US |
thesis.degree.discipline | Electrical and Computer Engineering | en_US |
thesis.degree.discipline | Graduate College | en_US |
thesis.degree.name | Ph.D. | en_US |
dc.description.note | This item was digitized from a paper original and/or a microfilm copy. If you need higher-resolution images for any content in this item, please contact us at repository@u.library.arizona.edu. | |
dc.description.admin-note | Original file replaced with corrected file October 2023. | |
refterms.dateFOA | 2018-07-17T23:46:25Z | |
html.description.abstract | The rising complexity of interconnect and packaging structures in VLSI systems has increased the necessity of applying modeling and simulation techniques for analysis and design. To effectively manage design data and CAD tools for modeling and simulations of electronic packaging, a framework which provides different levels of services is essential. This paper discusses a computer-aided design framework for the aforementioned purposes. A CAD framework with a five layered architecture is developed to support the analysis and design for VLSI packaging and interconnects. The first layer of the framework emphasizes the fundamental integration of CAD tools and simulation management. In the second layer of the architecture, design data representation and management are stressed. Two design databases termed the Chip Model Library and the Packaging Model Library are developed and coupled in this layer. We applied an object-oriented approach to implement libraries and encapsulate CAD tools. System level (board level) modeling and simulation are presented in the third layer of the framework. CMOS based multichip modules (MCMs) are used for our discussion. The fourth layer is for the automation of design process by coordinating different CAD tools. The highest layer in the proposed CAD framework is the level for design methodology management. A rule and frame based system is illustrated for simulation model generation of electronic packages. |