Evaluation of gallium arsenic(x) antimony(1-x)/indium(y) aluminum(1-y) arsenicp-channel HIGFETs for complementary technologies.
AuthorMartinez, Marino Juan.
Committee ChairGalloway, Kenneth F.
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PublisherThe University of Arizona.
RightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
AbstractThis work shows the viability of p-channel GaAsₓSb₁₋ₓ/In(y)Al(1-y)As HIGFETs for III-V compound-based complementary technologies to compete with silicon CMOS for specialized applications. Monte Carlo simulation was used to establish that even for the most extreme cases of alloy scattering GaAsₓSb₁₋ₓ on InP has a higher bulk hole mobility than GaAs. Process development demonstrated that H₂O:H₂O₂:H₃PO₄:L-tartaric acid-based etchant solutions provide a reliable etchant with a selectivity of approximately 2:1 of GaAsₓSb₁₋ₓ over In(y)Al(1-y)As. Process development also showed that Ti/Au was the most reliable gate metal for contact to In(y)Al(1-y)As and that care must be taken to avoid letting some common chemical solutions come into contact with GaAsₓSb₁₋ₓ. Experimental devices established that lattice-matched GaAsₓSb₁₋ₓ channel layers had low gate leakage currents, but had otherwise poor performance. However, experimental devices with strained GaSb-rich GaAsₓSb₁₋ₓ channels had the lowest recorded gate leakage current for a heterostructure FET yielding a gate turn-on voltage of -3 V and also had transconductance and current drive comparable to the best p-channel HIGFETs of any material systems to date. Finally, SPICE simulations showed that if integrated with n-channel HIGFETs with comparable gate leakage and moderate performance, modestly improved p-channel devices make possible technology with approximately half the delay time of similar CMOS circuits. Although silicon CMOS has enormous advantages over complementary HFETs in terms of robustness and yield which allow very high densities of integration, this work clearly establishes that this infant technology has the capability to challenge the more established CMOS on the basis of speed and power consumption.
Degree ProgramElectrical and Computer Engineering