Performance and area optimization in sea-of-wires array synthesis.
Committee ChairHill, Fredrick J.
MetadataShow full item record
PublisherThe University of Arizona.
RightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
AbstractThis dissertation addresses several techniques used for the layout optimization with respect to both delay and chip area of the Sea-of-Wires Array, a unique CMOS design methodology. SWAPSS, Sea-of-Wires Array Performance Sensitive Synthesis, is an automated design tool that maps the input RIF (RTL Intermediate Formate) specification onto the output SLF (Symbolic Layout Format) of Sea-of-Wires Array. The work described in the dissertation can be divided into four parts. The first part describes the improvement in the placement and interconnection of synthesis from previous work. The second part introduces techniques used for area optimization. Those techniques include logic simplification, gate re-ordering, column folding and row folding. The third part describes techniques like transistors sizing, buffer inserting and gate breaking that are used for performance optimization. A two-table delay approximation is used to facilitate a fast and accurate timing analysis. The avoiding of false paths introduced from control part of the design is done by passing the design information from high level (Register Transfer Level) to the timing analysis in the layout level. The results of several benchmarks are given in the last part of the dissertation. By comparing SWAPSS with other design methods, it shows that results from SWAPSS have better performance in most of the benchmark circuits.
Degree ProgramElectrical and Computer Engineering