Structuring VHDL synthesis using the AHPL paradigm.

Abstract

The widespread use of VHDL for RT synthesis in the design community and the problems associated with using the language for such a purpose is the driving force behind defining this research. Although VHDL includes constructs that can be useful in design representation, it will be demonstrated that synthesis from VHDL does not produce optimum results and is not computationally efficient. A number of real design scenarios will be analyzed and the pitfalls associated with each will be highlighted. The alternative is to use a language that is designed for synthesis and yet possesses all the representation power of VHDL. AHPL (A Hardware Programming Language) will be used for this purpose. Due to the one to one correspondence between AHPL constructs and the hardware primitives, derivation of hardware from the description is a natural process. Although AHPL has proved to be a robust and effective synthesis language, it requires modest extensions so that all models described in VHDL synthesis subsets can also be described in AHPL at the same level of abstraction as VHDL. The resulting language will be referred to as Extended AHPL or XAHPL for short. A synthesis methodology and implementation using XAHPL will be presented. Moreover, the results of synthesizing XAHPL and equivalent VHDL models under the same constraints and environment will be compared. This comparison can be interpreted as a cost metric for the VHDL synthesis methodology. Lastly, since many designers are and will be using VHDL for synthesis, a subset of VHDL which carries most correspondence with XAHPL will be defined.