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    Design tradeoffs for noise control in signal integrity for MOS-based interconnect systems.

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    Author
    Yang, Yaochao.
    Issue Date
    1995
    Committee Chair
    Brews, John R.
    
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    Publisher
    The University of Arizona.
    Rights
    Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
    Abstract
    Three design tradeoff relations for noise control, namely control for ground bounce noise, control for crosstalk noise, and control for reflection noise, in signal integrity for MOS-based systems are discussed here. Both long-channel modeled MOST (MOS1) and short-channel modeled MOST (MOS3) are used to derived tradeoffs between performance parameters and electrical parameters for a lumped modeled ground-path inductance. Quantitative expressions relating driver size, loading capacitance, edge speed of input signal, parasitic inductance, and a maximum number of allowable simultaneously switching drivers to the worst-case, maximum ground bounce and the signal switching (delay) time are shown to agree with SPICE simulations for both MOS1 and MOS3 devices. Dependent upon the strength of line coupling, two design guidelines to design interconnect systems for targets of 4% far-end overshoot, 10% far-end crosstalk, and a pre-specified far-end response time are introduced to upgrade package performance and packaging density. A low-frequency approximation associated with a second-order Butterworth response is the foundation to control far-end overshoot for the single-mode excitation, and/or for the mixed-mode excitation with weakly coupled lines. An average-transfer-function method is introduced for calculating the required output impedance of source (driver) when multiple modes are excited for strongly coupled lines. It is shown that the far-end response can be significantly improved with reliable operation if the output impedance is designed to be less than the line impedance according to the proposed approach. The near-end and the far-end crosstalk are derived for capacitive far-end and resistive (unmatched) near-end terminations on both the driven and the quiet lines. A simple far-end crosstalk estimate assuming a low line loss, weak line coupling, and a small capacitive load is first derived based on multiple reflections of backward coupling noise from mis-matched terminations. This simple estimate ensures controlled crosstalk for weakly coupled cases. Derivations in the frequency and the time domain of two limits, namely the high-frequency and the low-frequency approximation, for the far-end crosstalk then are followed for heavily-loaded, lossy lines, and/or strong line coupling. Compared to SPICE calculations, It is shown that these two limits can serve as a upper bound and a lower bound for the far-end crosstalk estimate. To estimate the signal delay time, a simple expression that combines the propagation delay time and the far-end Z(0)G(L) time is formulated first. The Elmore delay time for a single line provides a good delay estimate for a signal propagating on loosely coupled lines. For strongly coupled lines, a modified Elmore delay time with a coupling factor is derived, which agrees well with SPICE calculations. Design curves for targets of 4% far-end overshoot and 10% far-end crosstalk are given, and design guidelines, based on a second-order polynomial approximation and least-squares data fitting, are introduced for strongly-coupled lines. SPICE simulations for systems designed using these guidelines agree very well with the design targets, namely a 4% far-end overshoot and a 10% far-end crosstalk. Based upon the assumption that both unsealed and scaled systems satisfy the proposed design guidelines, possible scaling tradeoffs for down-sized (scaled) systems also are examined extensively.
    Type
    text
    Dissertation-Reproduction (electronic)
    Degree Name
    Ph.D.
    Degree Level
    doctoral
    Degree Program
    Electrical and Computer Engineering
    Graduate College
    Degree Grantor
    University of Arizona
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