Electrical effects of CMOS circuit packaging

Abstract

Integrated systems are becoming so complex, it is extremely difficult for designers to simulate full systems, particularly early in the design process. What the designer needs is a methodology to quickly look at where he/she is going, and determine if there are any potential packaging related problems. If so, where did the problem originate, and what can be done about it? The designer wants a quick, easy to use and understand methodology which consistently yields reasonably accurate results. This dissertation is limited to CMOS circuits interfacing with metal interconnects. Of particular interest here is the power and ground bounce, or noise, produced when large numbers of output drivers switch simultaneously. The high output voltage swing, wide range between best and worst case device performance, increased density, and high I/O counts of CMOS integrated circuits make them particularly susceptible to excessive simultaneous switching noise. A package model suitable for switching noise simulation is used to develop a simplified methodology for modeling and simulating power distribution networks in the presence of simultaneous switching outputs. This methodology is validated with specific circuit examples, and used to investigate simultaneous switching noise in detail. Of particular interest are the effects of various parameters on switching noise magnitude. This leads to the derivation and verification of a simple analytic switching noise formula, and a summary of noise reduction techniques. Output driver delay and switching noise performance, and parameters that effect performance are examined in detail. The use of damping resistance for switching noise reduction, including the limitations for high current drivers are discussed. An adaptive low noise driver is proposed, which drastically reduces simultaneous switching noise, while still meeting worst case delay specifications. The successful application of the switching noise modeling and simulation methodology in the designs of four released ASICs and two low noise packages are summarized. Finally, printed wiring board (PWB) electrical properties and general, simplified design guidelines are outlined. Two circuit examples are detailed, one dealing with a signal backplane, and the other a clock distribution network on a multi-layer PWB.