AN OPTIMIZATION STAGE FOR AHPL COMPILER (LAYOUT).

Abstract

The dissertation is a description of an analysis and a case study of an Optimization Stage for a Standard Cell oriented silicon compiler. Using the AHPL hardware description language, a complete representation hierarchy (functional, logic, and layout) is proposed for circuits defined at a Register Transfer level. The design of a new class of methods for layout analysis and optimization is based on this hierarchy. A layout evaluation method is based on the analysis of an activity graph derived from a circuit layout. The cost measure for such a graph is defined and used in evaluation of the necessary and sufficient conditions for design optimality (NSCDO). Iterations within the optimization process are controlled using a synthetic measure derived from these optimality conditions. A proposed layout optimization heuristic, derived from NSCDO, allows for better routing channel area utilization without compromising a circuit's timing performance. It is based on an analysis of the timing behavior modifications introduced by the various materials used as interconnectors resulting in an improvement of the load dependency of the output driving capabilities of cells. The dissertation contains an example of a quantitative analysis of a CMOS digital circuit. A system implementing some of the algorithms described above has been written in FORTRAN77.