LPCVD TUNGSTEN MULTILAYER METALLIZATION FOR VLSI SYSTEMS.

Abstract

Advances in microlithography, dry etching, scaling of devices, ion-implantation, process control, and computer aid design brought the integrated circuit technology into the era of VLSI circuits. Those circuits are characterized by high packing density, improved performance, complex circuits, and large chip sizes. Interconnects and their spacing dominate the chip area of VLSI circuits and they degrade the circuit performance through the unacceptable high time delays. Multilayer metallization enables shorter interconnects, ease of design and yet higher packing density for VLSI circuits. It was shown in this dissertation that, tungsten films deposited in a cold-wall LPCVD reactor offer viable solution to the problems of VLSI multilayer interconnects. Experiments showed that LPCVD tungsten films have good uniformity, high purity, low resistivity, low stress-good adherence and are readily patterned into high resolution lines. Moreover, a multilayer interconnect system consisting of three layers of tungsten metallization followed by a fourth layer of aluminum metallization has been designed, fabricated and tested. The interlevel dielectric used to separate the metal layers was CVD phosphorus doped silicon dioxide. Low ohmic contacts were achieved for heavily doped silicon. Also, low resistance tungsten-tungsten intermetallic contacts were obtained. In addition to excellent step coverage, high electromigration resistance of interconnects was realized. Finally, CMOS devices and logic gates were successfully fabricated and tested using tungsten multilayer metallization schemes.