Microarchitecture and Compiler Techniques for Dual Width ISA Processors

Abstract

Embedded processors have to execute programs under the constraints of limited resources such as memory and power. As a result, code size becomes as important a metric as performance when evaluating applications written for the embedded domain. Existing techniques improve one program metric at the cost of the other. Simultaneouslyachieving good code size and performance is a challenging problem. This dissertation proposes compiler and microarchitectural techniquesthat address this problem.Dual-Width ISA processors provide a platform with two instructionsets - a 32-bit instruction set yielding fast programs and a 16-bit instruction set yielding small programs. The techniques described here exploit properties of dual-width ISA processors to bridge the gap betweenthe small programs and the fast programs by improving the performance of 16-bit programs, yielding small {\em and} fast programs.An integrated microarchitectural/compiler framework (Dynamic InstructionCoalescing) and a purely microarchitectural framework (Dynamic Eager Execution) are proposed. Dynamic Instruction Coalescing introduces a new kindof instruction - an Augmenting eXtension or AX. AX instructions aredynamically coalesced with the succeeding instruction at no cost. Efficient compiler techniques are proposed to use AX instructions to perform localand global optimizations that improve performance without negatively affectingcode size. Dynamic Eager Execution is a microarchitecture that improves the performance of 16-bit programs by eagerly executing instructions. This framework comprises two techniques namely Dynamic Delayed Branching and Dynamic 2-wide Execution. The first improves branch behavior and the otherseeks to improve program execution by simultaneously issuing multiple instructions.