ROBUST DEVICE MODELING WITH PROCESS VARIATION CONSIDERATION AND DIMENSION REDUCTION TECHNIQUES
Committee ChairWang, Janet
MetadataShow full item record
PublisherThe University of Arizona.
RightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
AbstractNowadays the highest device integration affects the design process in several ways. The process variations (PV) significantly impact the circuit performance. As a consequence, a major consideration is determining the relation of the production yield to the technology based manufacturing variations. The traditional Monte Carlo based sampling analysis became computationally not effective due to employing complex device models with the large parameter set. The higher device integration requires dealing with numerous local and global parameters and can bottleneck the efforts of achieving fast design cycles.Statistical analysis can be facilitated by direct relation estimation a of circuit metrics to the set of PV parameters. The traditional transistor models use a large number of parameters and equations but various performance factors are possible to be related to small parameter set. A new macro model is proposed for CMOS complementary gates, where all static and dynamic characteristics are related to set of Finite Points of IV device curves. All timing and power related quantities can be predicted by evaluating the model equations. The dynamic characterization relies on charge distribution at each node. The affect of all PV is represented with characterizing the FP sensitivity. In overall the new gate model employ same computational structure for different devices in far more simple computational form.Large scale circuit analysis based on the FP models can be used for estimation of various global performance parameters. Timing performance (STA) is calculated from node to node, where at each step a new set of parameters (including PV) are introduced. Motivated by the limitations the traditional PCA, we simplify the overall computational cost with new efficient reduction technique. It turned out that the input output correlation of performance-parameters model is essential information for reduction. If the model is unknown, Sliced Inverse Regression (SIR) technique can be used to determine the Effective Reduction Space (e.d.r.). Optionally if the empiric performance analytic expression is known, the e.d.r. is found by Principle Hessian Method. In theoretical aspect the inverse reduction technique reduces parameters in the sense of their statistical significance.
Degree ProgramElectrical & Computer Engineering