Development of Modeling, Simulation and Measurement Methodologies for Signal Integrity Analysis of High-Speed Packaging Interconnects

Abstract

As chip complexity and speed continue to increase, the packaging interconnects increasingly affect the performance of the electrical systems. Signal integrity analysis becomes exceedingly complex and important. The primary goal of this research is in-depth understanding of the signal integrity issue in high-speed chips and electronic systems, and development of modeling, simulation, and measurement methodologies for accurate and efficient characterization or prediction of the electrical characteristics of these on-chip and on-substrate packaging interconnects. The research is focused on three parts. First, a new broadband measurement method is proposed to determine the complex material properties of the dielectric materials in "as-packaged" environments, and to extract the frequency dependant RLGC parameters of the packaging interconnects. Second, a broadband CPW to microstrip via-less transition is developed to facilitate on-wafer measurement of microstrip based packaging structures. Third, microstrip lines over gridded ground plane are studied. Methodologies are proposed to efficiently simulate these structures in the frequency domain and time domain. SPICE compatible lumped-element models are developed. The methodologies and the lumped element models are verified by frequency domain and time domain measurement.