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dc.contributor.advisorMelde, Kathleen L.en_US
dc.contributor.authorLi, Qian.
dc.creatorLi, Qian.en_US
dc.date.accessioned2012-01-17T17:59:29Z
dc.date.available2012-01-17T17:59:29Z
dc.date.issued2011
dc.identifier.urihttp://hdl.handle.net/10150/203472
dc.description.abstractThe development of modern digital communication systems has been entered a new era with faster signal transmission and processing capability, called high-speed circuit systems. As their clock frequencies have increased and rise times of signals have decreased, the signal integrity of interconnects in the packaging and printed circuit boards plays a more and more important role. In high-speed circuit systems, the well-designed logic functions most likely will not work well if their interconnects are not taken into account.This dissertation addresses to profoundly understand the signal integrity knowledge, be proficient in calculation, simulation and measurements, and be capable of solving related signal integrity problems. The research mainly emphasizes on three aspects. First of all, the impact of on-wafer calibration methods on the measured results of coplanar waveguide circuits is comprehensively investigated, with their measurement repeatability and accuracy. Furthermore, a method is presented to characterize the physically-consistent broadband material properties for both rigid and flexible dielectric materials. Last but not least, a hybrid method for efficient modeling of three dimensional via structures is developed, in order to simplify the traditional 3D full-length via simulations and dramatically reduce the via build and simulation time and complexity.
dc.language.isoenen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectSignal Integrityen_US
dc.subjectVia modelingen_US
dc.subjectElectrical & Computer Engineeringen_US
dc.subjectMaterial Characterizationen_US
dc.subjecton-wafer measurmenten_US
dc.titleSIGNAL INTEGRITY ANALYSIS ON MATERIALS AND VIA STRUCTURES MODELING AND CHARACTERIZATIONen_US
dc.typetexten_US
dc.typeElectronic Dissertationen_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.leveldoctoralen_US
dc.contributor.committeememberDvorak, Steven L.en_US
dc.contributor.committeememberWang Roveda, Janet M.en_US
dc.contributor.committeememberMelde, Kathleen L.en_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical & Computer Engineeringen_US
thesis.degree.namePh.D.en_US
refterms.dateFOA2018-08-25T21:36:43Z
html.description.abstractThe development of modern digital communication systems has been entered a new era with faster signal transmission and processing capability, called high-speed circuit systems. As their clock frequencies have increased and rise times of signals have decreased, the signal integrity of interconnects in the packaging and printed circuit boards plays a more and more important role. In high-speed circuit systems, the well-designed logic functions most likely will not work well if their interconnects are not taken into account.This dissertation addresses to profoundly understand the signal integrity knowledge, be proficient in calculation, simulation and measurements, and be capable of solving related signal integrity problems. The research mainly emphasizes on three aspects. First of all, the impact of on-wafer calibration methods on the measured results of coplanar waveguide circuits is comprehensively investigated, with their measurement repeatability and accuracy. Furthermore, a method is presented to characterize the physically-consistent broadband material properties for both rigid and flexible dielectric materials. Last but not least, a hybrid method for efficient modeling of three dimensional via structures is developed, in order to simplify the traditional 3D full-length via simulations and dramatically reduce the via build and simulation time and complexity.


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