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High-speed Multiplier Design Using Multi-Operand Multipliers

dc.contributor.authorNezhad, Mohammad Reza Reshadi
dc.contributor.authorNavi, Kaivan
dc.date.accessioned2012-04-20T02:28:15Z
dc.date.available2012-04-20T02:28:15Z
dc.date.issued2012-04-01
dc.identifier.issn2277–5420
dc.identifier.urihttp://hdl.handle.net/10150/219513
dc.descriptionMultipliers are used in most arithmetic computing systems such as 3D graphics, signal processing, and etc. It is inherently a slow operation as a large number of partial products are added to produce the result. There has been much work done on designing multipliers [1]-[6]. In first stage, Multiplication is implemented by accumulation of partial products, each of which is conceptually produced via multiplying the whole multi-digit multiplicand by a weighted digit of multiplier. To compute partial products, most of the approaches employ the Modified Booth Encoding (MBE) approach [3]-[5], [7], for the first step because of its ability to cut the number of partial products rows in half. In next step the partial products are reduced to a row of sums and a row of caries which is called reduction stage.en_US
dc.description.abstractMultiplication is one of the major bottlenecks in most digital computing and signal processing systems, which depends on the word size to be executed. This paper presents three deferent designs for three-operand 4-bit multiplier for positive integer multiplication, and compares them in regard to timing, dynamic power, and area with classical method of multiplication performed on today architects. The three-operand 4-bit multipliers structure introduced, serves as a building block for three-operand multipliers in general
dc.language.isoenen_US
dc.publisherIJCSNen_US
dc.relation.ispartofseriesIJCSN-2012-1-2-9en_US
dc.relation.urlhttp://ijcsn.org/publications.htmlen_US
dc.subjectDadda's multiplieren_US
dc.subjectdigital multipliersen_US
dc.subjectfast multipliersen_US
dc.subjectparallel multipliersen_US
dc.subjectWallace's multipliersen_US
dc.titleHigh-speed Multiplier Design Using Multi-Operand Multipliersen_US
dc.typeArticleen_US
dc.typeTechnical Reporten_US
dc.contributor.departmentDepartment of Electrical and Computer engineering, Shahid Beheshti University, G.C., Tehran, Tehran 1983963113, Iranen_US
dc.contributor.departmentFaculty of Department of Computer engineering, University of Isfahan, Isfahan, Isfahan 8174673440, Iranen_US
dc.identifier.journalInternational Journal of Computer Science and Networken_US
refterms.dateFOA2018-08-13T15:07:31Z
html.description.abstractMultiplication is one of the major bottlenecks in most digital computing and signal processing systems, which depends on the word size to be executed. This paper presents three deferent designs for three-operand 4-bit multiplier for positive integer multiplication, and compares them in regard to timing, dynamic power, and area with classical method of multiplication performed on today architects. The three-operand 4-bit multipliers structure introduced, serves as a building block for three-operand multipliers in general


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