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dc.contributor.authorKelly, Richard Thevenet.
dc.creatorKelly, Richard Thevenet.en_US
dc.date.accessioned2013-03-21T11:59:57Zen
dc.date.available2013-03-21T11:59:57Zen
dc.date.issued1985en_US
dc.identifier.urihttp://hdl.handle.net/10150/275385en
dc.language.isoen_USen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectPrinted circuits -- Testing.en_US
dc.titleDETERMINING COST EFFECTIVE TEST FLOWS FOR DIGITAL PRINTED CIRCUIT BOARDS.en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.identifier.oclc14061759en_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.levelmastersen_US
dc.identifier.proquest1326380en_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.nameM.S.en_US
dc.identifier.bibrecord.b15665343en_US
refterms.dateFOA2018-08-27T06:33:14Z


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