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dc.contributor.authorChen, Daven, 1959-
dc.creatorChen, Daven, 1959-en_US
dc.date.accessioned2013-03-21T12:06:48Z
dc.date.available2013-03-21T12:06:48Z
dc.date.issued1986en_US
dc.identifier.urihttp://hdl.handle.net/10150/275572
dc.language.isoen_USen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectIntegrated circuits -- Testing.en_US
dc.subjectLogic circuits -- Testing.en_US
dc.titleCOMPARISON OF SCIRTSS EFFICIENCY WITH D-ALGORITHM APPLICATION TO ITERATIVE NETWORKS (TEST).en_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.identifier.oclc15581670en_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.levelmastersen_US
dc.identifier.proquest1328485en_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.nameM.S.en_US
dc.identifier.bibrecord.b15946393en_US
refterms.dateFOA2018-08-27T07:30:16Z


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