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    PERFORMANCE OF HIERARCHICALLY FLEXIBLE ADAPTIVE COMPUTER ARCHITECTURE APPLIED TO SORTING PROBLEMS

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    azu_td_1331399_sip1_m.pdf
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    Author
    Ferng, Ming-Jehn, 1958-
    Issue Date
    1987
    Keywords
    Computer architecture.
    Computer simulation.
    Sorting (Electronic computers)
    
    Metadata
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    Publisher
    The University of Arizona.
    Rights
    Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
    Abstract
    In this thesis existing models of adaptive computer architecture were modified to adapt actual sorting problems to "divide 'n' conquer" (DQ) coordinator type configuration in which the children processors were expanded from three to four. Two hire/fire strategies, one using packets waiting in queue and the other using the average turn around time, were applied to maintain the hierarchical tree structure. More than 1200 simulation runs were analyzed and compared, finding that the first strategy was best at fast packet arrival rate and the second strategy was best at slow packets arrival rate. Comparing the hire/fire signal generation policies, the "fc-root" was best and the "root-fp" was worst. While comparing the effect of variable weighting factors in processors, using smaller weighting factor in either "partitioner" for the first strategy or "f-computer" for the second strategy may improve the system performance. (Abstract shortened with permission of author.)
    Type
    text
    Thesis-Reproduction (electronic)
    Degree Name
    M.S.
    Degree Level
    masters
    Degree Program
    Graduate College
    Electrical and Computer Engineering
    Degree Grantor
    University of Arizona
    Collections
    Master's Theses

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