ALTERNATE SCREENING PROCEDURES FOR SEMICONDUCTOR VISUAL INSPECTION
| dc.contributor.author | Guarin, Fernando, 1954- | |
| dc.creator | Guarin, Fernando, 1954- | en_US |
| dc.date.accessioned | 2013-03-28T10:05:35Z | en |
| dc.date.available | 2013-03-28T10:05:35Z | en |
| dc.date.issued | 1987 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10150/276463 | en |
| dc.description.abstract | A sequence of electrical tests was developed to provide a viable alternative to the performance of high magnification visual inspection for high reliability integrated circuits in a large volume production environment. The primary approach was based on: close monitoring of the Substrate-N epi I-V characteristics, voltage overstress exposure and subsequent verification of the devices' low level leakage and thermal response. This method was implemented and evaluated for the specific case of a 16K Bipolar Schottky PROM. Reliability tests indicated that devices processed using the proposed alternate screen sequence achieved failure rates as low as those obtained using high magnification visual inspection. | |
| dc.language.iso | en_US | en_US |
| dc.publisher | The University of Arizona. | en_US |
| dc.rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | en_US |
| dc.subject | Integrated circuits -- Testing. | en_US |
| dc.subject | Semiconductors -- Testing. | en_US |
| dc.subject | Electric testing. | en_US |
| dc.title | ALTERNATE SCREENING PROCEDURES FOR SEMICONDUCTOR VISUAL INSPECTION | en_US |
| dc.type | text | en_US |
| dc.type | Thesis-Reproduction (electronic) | en_US |
| dc.identifier.oclc | 17576197 | en_US |
| thesis.degree.grantor | University of Arizona | en_US |
| thesis.degree.level | masters | en_US |
| dc.identifier.proquest | 1331404 | en_US |
| thesis.degree.discipline | Graduate College | en_US |
| thesis.degree.discipline | Electrical and Computer Engineering | en_US |
| thesis.degree.name | M.S. | en_US |
| dc.identifier.bibrecord | .b16337268 | en_US |
| refterms.dateFOA | 2018-06-12T07:22:11Z | |
| html.description.abstract | A sequence of electrical tests was developed to provide a viable alternative to the performance of high magnification visual inspection for high reliability integrated circuits in a large volume production environment. The primary approach was based on: close monitoring of the Substrate-N epi I-V characteristics, voltage overstress exposure and subsequent verification of the devices' low level leakage and thermal response. This method was implemented and evaluated for the specific case of a 16K Bipolar Schottky PROM. Reliability tests indicated that devices processed using the proposed alternate screen sequence achieved failure rates as low as those obtained using high magnification visual inspection. |
