THE IMPLEMENTATION OF THE HIERARCHICAL ABSTRACT SIMULATOR ON THE IPSC COMPUTER

Abstract

The hierarchical abstract simulator is a multicomponent, multilevel discrete event model where each processor communicates with other processors by message passing. A methodology was developed to map the hierarchical abstract simulator onto distributed simulator architectures. The Intel's Personal Super Computer (iPSC) family with a concurrent-processing architecture is well suited for such simulation implementation. This thesis presents an alternative mapping realization of the hierarchical abstract simulator by using Intel's FORTRAN 286, FORTRAN 77 with extensions, on the iPSC computer (Hypercube). Algorithms for the hierarchical abstract simulator are provided in high level pseudo codes. A summary of iPSC system overview and programming concepts is described. Also, two examples are given for the illustration of our hypercube implementation. Finally, some experimental runs were made on the implementation, and comparisons of the performance (execution time) between sequential and parallel processor assignment are made.