The evaluation of the PODEM algorithm as a mechanism to generate goal states for a sequential circuit test search
Issue Date
1988Keywords
Electric circuits -- Testing.Algorithms.
Integrated circuits -- Very large scale integration -- Testing.
Advisor
Hill, FredrickMetadata
Show full item recordPublisher
The University of Arizona.Rights
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.Abstract
In a VLSI design environment, a more efficient test generation algorithm is definitely needed. This thesis evaluates a test generation algorithm, PODEM, as mechanism to generate the goal states in a sequential circuit test search system, SCIRTSS. First, a hardware description language, AHPL, is used to describe the behavior of a sequential circuit. Next, SCIRTSS is used to generate the test vectors. Several circuits are evaluated and experimental results are compared with data from a previous version of SCIRTSS which was implemented with the D-Algorithm. Depending on the number of reconvergent fanouts in a circuit, it is found that PODEM is 1 to 23 times faster than the D-Algorithm.Type
textThesis-Reproduction (electronic)
Degree Name
M.S.Degree Level
mastersDegree Program
Graduate CollegeElectrical and Computer Engineering