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dc.contributor.advisorHill, Fredricken_US
dc.contributor.authorLee, Hoi-Ming Bonny, 1961-
dc.creatorLee, Hoi-Ming Bonny, 1961-en_US
dc.date.accessioned2013-03-28T10:15:15Z
dc.date.available2013-03-28T10:15:15Z
dc.date.issued1988en_US
dc.identifier.urihttp://hdl.handle.net/10150/276730
dc.description.abstractIn a VLSI design environment, a more efficient test generation algorithm is definitely needed. This thesis evaluates a test generation algorithm, PODEM, as mechanism to generate the goal states in a sequential circuit test search system, SCIRTSS. First, a hardware description language, AHPL, is used to describe the behavior of a sequential circuit. Next, SCIRTSS is used to generate the test vectors. Several circuits are evaluated and experimental results are compared with data from a previous version of SCIRTSS which was implemented with the D-Algorithm. Depending on the number of reconvergent fanouts in a circuit, it is found that PODEM is 1 to 23 times faster than the D-Algorithm.
dc.language.isoen_USen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectElectric circuits -- Testing.en_US
dc.subjectAlgorithms.en_US
dc.subjectIntegrated circuits -- Very large scale integration -- Testing.en_US
dc.titleThe evaluation of the PODEM algorithm as a mechanism to generate goal states for a sequential circuit test searchen_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.identifier.oclc20975053en_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.levelmastersen_US
dc.identifier.proquest1333602en_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.nameM.S.en_US
dc.identifier.bibrecord.b17129680en_US
refterms.dateFOA2018-06-16T04:57:38Z
html.description.abstractIn a VLSI design environment, a more efficient test generation algorithm is definitely needed. This thesis evaluates a test generation algorithm, PODEM, as mechanism to generate the goal states in a sequential circuit test search system, SCIRTSS. First, a hardware description language, AHPL, is used to describe the behavior of a sequential circuit. Next, SCIRTSS is used to generate the test vectors. Several circuits are evaluated and experimental results are compared with data from a previous version of SCIRTSS which was implemented with the D-Algorithm. Depending on the number of reconvergent fanouts in a circuit, it is found that PODEM is 1 to 23 times faster than the D-Algorithm.


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