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    Surface and geometrical effect on the punch-through device

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    Author
    Liu, Bin, 1957-
    Issue Date
    1988
    Keywords
    Planar transistors.
    Integrated circuits.
    Semiconductors.
    Advisor
    Mattson, Roy H.
    
    Metadata
    Show full item record
    Publisher
    The University of Arizona.
    Rights
    Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
    Abstract
    The punch-through space-charge-limited load (PTSCLL) may be an alternate VLSI design as a high resistance load device. A surface and geometrical study on the PTSCLL device is presented. From this research, it is found out that the dynamic resistance value increases as the surface bias to a negatively voltage. Also, the resistance increases as the channel length and substrate doping increase. But the resistance value decreases as the channel width, junction depth, and overlap oxide thickness increase. Incorporate these design considerations, it can maximize the resistance value of the PTSCLL.
    Type
    text
    Thesis-Reproduction (electronic)
    Degree Name
    M.S.
    Degree Level
    masters
    Degree Program
    Graduate College
    Electrical and Computer Engineering
    Degree Grantor
    University of Arizona
    Collections
    Master's Theses

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