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Analysis of approaches to synchronous faults simulation by surrogate propagation
| dc.contributor.advisor | Hill, Fredrick J. | en_US |
| dc.contributor.author | Lee, Chang-Hwa, 1957- | |
| dc.creator | Lee, Chang-Hwa, 1957- | en_US |
| dc.date.accessioned | 2013-03-28T10:16:42Z | |
| dc.date.available | 2013-03-28T10:16:42Z | |
| dc.date.issued | 1988 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10150/276771 | |
| dc.description.abstract | This thesis describes a new simulation technique, Synchronous Faults Simulation by Surrogate with Exception, first proposed by Dr. F. J. Hill and has been initiated under the direction of Xiolin Wang. This paper reports early results of that project. The Sequential Circuit Test Sequence System, SCIRTSS, is an automatic test generation system which is developed in University of Arizona which will be used as a target to compare against the results of the new simulator. The major objective of this research is to analyze the results obtained by using the new simulator SFSSE against the results obtained by using the parallel simulator SCIRTSS. The results are listed in this paper to verify superiority of the new simulation technique. | |
| dc.language.iso | en_US | en_US |
| dc.publisher | The University of Arizona. | en_US |
| dc.rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | en_US |
| dc.subject | Digital electronics -- Testing. | en_US |
| dc.subject | Computer networks -- Simulation methods. | en_US |
| dc.title | Analysis of approaches to synchronous faults simulation by surrogate propagation | en_US |
| dc.type | text | en_US |
| dc.type | Thesis-Reproduction (electronic) | en_US |
| dc.identifier.oclc | 21217969 | en_US |
| thesis.degree.grantor | University of Arizona | en_US |
| thesis.degree.level | masters | en_US |
| dc.identifier.proquest | 1334301 | en_US |
| thesis.degree.discipline | Graduate College | en_US |
| thesis.degree.discipline | Electrical and Computer Engineering | en_US |
| thesis.degree.name | M.S. | en_US |
| dc.identifier.bibrecord | .b17188532 | en_US |
| refterms.dateFOA | 2018-06-23T13:07:25Z | |
| html.description.abstract | This thesis describes a new simulation technique, Synchronous Faults Simulation by Surrogate with Exception, first proposed by Dr. F. J. Hill and has been initiated under the direction of Xiolin Wang. This paper reports early results of that project. The Sequential Circuit Test Sequence System, SCIRTSS, is an automatic test generation system which is developed in University of Arizona which will be used as a target to compare against the results of the new simulator. The major objective of this research is to analyze the results obtained by using the new simulator SFSSE against the results obtained by using the parallel simulator SCIRTSS. The results are listed in this paper to verify superiority of the new simulation technique. |
