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dc.contributor.advisorSchrimpf, Ronald D.en_US
dc.contributor.authorSong, Shiunn Luen Steven, 1960-
dc.creatorSong, Shiunn Luen Steven, 1960-en_US
dc.date.accessioned2013-03-28T10:20:58Z
dc.date.available2013-03-28T10:20:58Z
dc.date.issued1988en_US
dc.identifier.urihttp://hdl.handle.net/10150/276882
dc.description.abstractThe LAMBDA-DIODE was invented in integrated-circuit form in 1974. There was a proposal about this device's application in memory circuits at that time. This thesis is to evaluate the circuit performance of the COMPLEMENTARY JFET LAMBDA-DIODE SRAM. It investigates the speed, power consumption and chip area of this circuit compared with the JFET CROSS COUPLED SRAM by using SPICE and breadboard simulation techniques. The results show positive signs of the Λ-DIODE's feasibility for use in VLSI static memory circuits from the chip area aspect if the parasitic capacitance of the JFET device could be minimized to reduce the power delay product.
dc.language.isoen_USen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectJunction transistors.en_US
dc.subjectField-effect transistors.en_US
dc.subjectIntegrated circuits -- Design.en_US
dc.titleCharacterization and design of the complementary JFET LAMBDA-DIODE SRAMen_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.identifier.oclc22499577en_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.levelmastersen_US
dc.identifier.proquest1335701en_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.nameM.S.en_US
dc.identifier.bibrecord.b17444457en_US
refterms.dateFOA2018-09-04T03:01:28Z
html.description.abstractThe LAMBDA-DIODE was invented in integrated-circuit form in 1974. There was a proposal about this device's application in memory circuits at that time. This thesis is to evaluate the circuit performance of the COMPLEMENTARY JFET LAMBDA-DIODE SRAM. It investigates the speed, power consumption and chip area of this circuit compared with the JFET CROSS COUPLED SRAM by using SPICE and breadboard simulation techniques. The results show positive signs of the Λ-DIODE's feasibility for use in VLSI static memory circuits from the chip area aspect if the parasitic capacitance of the JFET device could be minimized to reduce the power delay product.


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