Show simple item record

dc.contributor.authorJafar, Mutaz, 1960-
dc.creatorJafar, Mutaz, 1960-en_US
dc.date.accessioned2013-03-28T10:23:42Z
dc.date.available2013-03-28T10:23:42Z
dc.date.issued1986en_US
dc.identifier.urihttp://hdl.handle.net/10150/276959
dc.language.isoen_USen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectIntegrated circuits -- Very large scale integration.en_US
dc.titleTHERMAL MODELING/SIMULATION OF LEVEL 1 AND LEVEL 2 VLSI PACKAGINGen_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.identifier.oclc16749836en_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.levelmastersen_US
dc.identifier.proquest1329492en_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.nameM.S.en_US
dc.identifier.bibrecord.b16141696en_US
refterms.dateFOA2018-06-28T22:48:24Z


Files in this item

Thumbnail
Name:
azu_td_1329492_sip1_m.pdf
Size:
2.958Mb
Format:
PDF

This item appears in the following Collection(s)

Show simple item record