AdvisorHill, Fredrick J.
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PublisherThe University of Arizona.
RightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
AbstractIn the growing field of digital system design, there is a great need for design tools that will assist the engineer in developing large scale systems. AHPL, A Hardware Programming Language, is a hardware description language which allows a digital system to be described, evaluated, and analyzed. But like many design tools, AHPL cannot satisfy the multitude of design tool applications. In order to enhance the power of AHPL as a design tool, an EDIF translator is developed. The EDIF translator generates an EDIF netlist of an AHPL design, thus making it possible to port AHPL designs to other design tools.
Degree ProgramGraduate College
Electrical & Computer Engineering