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dc.contributor.advisorHill, Fredrick J.en_US
dc.contributor.authorSlipp, Walter Whitfield, 1964-
dc.creatorSlipp, Walter Whitfield, 1964-en_US
dc.date.accessioned2013-03-28T10:25:42Zen
dc.date.available2013-03-28T10:25:42Zen
dc.date.issued1989en_US
dc.identifier.urihttp://hdl.handle.net/10150/277016en
dc.description.abstractHardware description languages provide digital system designers with a convenient, compact method for describing complex circuits. A Hardware Programming Language (AHPL) is a powerful description language based on the APL programming language. AHPL circuit descriptions can be unambiguously translated into a logic gate network using the HPCOM hardware compiler. The initial discussion section covers the conversion of the VAX version of HPCOM into a version which will run on MS-DOS microcomputers. The major portion of the research focuses on the development, use, and application of a graphics display tool for HPCOM-generated networks. The display package, SUBGRAPH, allows selected subgraphs of a network to be viewed and/or printed. The discussion of this research concludes with an extensive example of the complete circuit generation and graphics display sequence. The printed graphics examples feature cases of particular interest for test generation.
dc.language.isoen_USen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectComputer hardware description languages.en_US
dc.subjectElectronic digital computers -- Design and construction -- Data processing.en_US
dc.titleDisplay of arbitrary subgraphs for HPCOM-generated networksen_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
dc.identifier.oclc22895136en_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.levelmastersen_US
dc.identifier.proquest1336905en_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical and Computer Engineeringen_US
thesis.degree.nameM.S.en_US
dc.identifier.bibrecord.b1752507xen_US
refterms.dateFOA2018-06-23T22:37:12Z
html.description.abstractHardware description languages provide digital system designers with a convenient, compact method for describing complex circuits. A Hardware Programming Language (AHPL) is a powerful description language based on the APL programming language. AHPL circuit descriptions can be unambiguously translated into a logic gate network using the HPCOM hardware compiler. The initial discussion section covers the conversion of the VAX version of HPCOM into a version which will run on MS-DOS microcomputers. The major portion of the research focuses on the development, use, and application of a graphics display tool for HPCOM-generated networks. The display package, SUBGRAPH, allows selected subgraphs of a network to be viewed and/or printed. The discussion of this research concludes with an extensive example of the complete circuit generation and graphics display sequence. The printed graphics examples feature cases of particular interest for test generation.


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