Fault tolerance and reconfiguration strategies for tree architectures

Abstract

Reconfigurable binary tree architectures have been widely studied and used in various VLSI implementations. These fault tolerance approaches can be classified into two categories. In thesis, we propose a fault diagnosis for the first category. Then a new block-oriented fault tolerance scheme for tree architectures is presented for the second category. The fundamental idea is to extend each single PE node in the tree to a block. Each block could consist of several PEs and the associated interconnection links. It is shown that several previous fault tolerant designs in the literature are special cases of the proposed design. The VLSI layout of binary tree is very efficient and the problem of long interconnections in other designs has been alleviated. Efficient reconfiguration algorithms and analysis are also presented.