Simulation, design, fabrication, and application of an electrostatic-discharge detector using a floating-gate transistor

Abstract

Electro-Static Discharge (ESD) problems in the semiconductor industry are exacerbated by the lack of information about the magnitudes of these events and their locations. This thesis describes an integrated device, similar in structure to an EEP-ROM cell, capable of measuring the magnitudes and polarities of electrostatic discharges. A quantitative formulation of the transfer characteristic of the device as a function of the design parameters and the subsequent layout, manufacturing and evaluation of this detector was obtained. A chip was fabricated which included experiments to test the presented mathematical model and its extensive range of sensitivity, as well as several structures to evaluate the use of this detector in industrial environments. Extensive use of computers helped in the process design and in the simulation of the non-linear model for the operation.