Locating logic design errors via test generation and don't-care propagation

Abstract

This thesis presents a new technique, the don't-care propagation method, for logic design verification and functional error location in which a gate-level implementation of a circuit is compared with a functional-level specification. In this method, test pattern set which is generated to detect single stuck-line faults in the gate-level implementation, are used to compare the gate-level implementation with the functional-level specification. In the presence of logic design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistency that may exit between the functional-level specification and the gate-level implementation. The proposed technique determines the region which contains the function error. This method has very high resolution that the region usually contains a single gate or a line and therefore, reduces the time required for debugging by the designers.