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dc.contributor.advisorKuo, Sy-Yenen_US
dc.contributor.authorHsu, Yaw-Dong, 1959-
dc.creatorHsu, Yaw-Dong, 1959-en_US
dc.date.accessioned2013-04-03T13:03:32Z
dc.date.available2013-04-03T13:03:32Z
dc.date.issued1991en_US
dc.identifier.urihttp://hdl.handle.net/10150/277847
dc.description.abstractThis thesis presents a new technique, the don't-care propagation method, for logic design verification and functional error location in which a gate-level implementation of a circuit is compared with a functional-level specification. In this method, test pattern set which is generated to detect single stuck-line faults in the gate-level implementation, are used to compare the gate-level implementation with the functional-level specification. In the presence of logic design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistency that may exit between the functional-level specification and the gate-level implementation. The proposed technique determines the region which contains the function error. This method has very high resolution that the region usually contains a single gate or a line and therefore, reduces the time required for debugging by the designers.
dc.language.isoen_USen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectEngineering, Electronics and Electrical.en_US
dc.titleLocating logic design errors via test generation and don't-care propagationen_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.levelmastersen_US
dc.identifier.proquest1343612en_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.nameM.S.en_US
dc.identifier.bibrecord.b26807087en_US
refterms.dateFOA2018-06-04T15:12:27Z
html.description.abstractThis thesis presents a new technique, the don't-care propagation method, for logic design verification and functional error location in which a gate-level implementation of a circuit is compared with a functional-level specification. In this method, test pattern set which is generated to detect single stuck-line faults in the gate-level implementation, are used to compare the gate-level implementation with the functional-level specification. In the presence of logic design errors, such a test set will produce responses in the implementation that disagree with the responses in the specification. In the verification phase of the design of logic circuits using the top-down approach, it is necessary not only to detect but also to locate the source of any inconsistency that may exit between the functional-level specification and the gate-level implementation. The proposed technique determines the region which contains the function error. This method has very high resolution that the region usually contains a single gate or a line and therefore, reduces the time required for debugging by the designers.


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