Framework for CMOS standard cell realization of AHPL descriptions
| dc.contributor.author | Jepperson, Brian, 1967- | |
| dc.creator | Jepperson, Brian, 1967- | en_US |
| dc.date.accessioned | 2013-04-03T13:09:54Z | |
| dc.date.available | 2013-04-03T13:09:54Z | |
| dc.date.issued | 1991 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10150/278017 | |
| dc.description.abstract | Hardware description languages can be powerful tools in creating digital system designs. AHPL, A Hardware Programming Language, is a hardware description language that simplifies the task of designing a digital system. One of the major problems in using a hardware description language is interfacing with commercially available simulation and layout tools. Many commercial tools use the Electronic Design Interchange Format (EDIF) in order to communicate designs. This thesis describes the AHPL to EDIF Netlist Translator (AENT) program. By using AENT, a designer can write an AHPL description, verify the design with a function level simulator, and generate a CMOS standard cell layout using a commercial layout tool. A post layout gate level simulation can also be performed to verify timing constraints. Several layout examples are given in this thesis, and results are compared with the Berkeley Synthesis System. | |
| dc.language.iso | en_US | en_US |
| dc.publisher | The University of Arizona. | en_US |
| dc.rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | en_US |
| dc.subject | Engineering, Electronics and Electrical. | en_US |
| dc.title | Framework for CMOS standard cell realization of AHPL descriptions | en_US |
| dc.type | text | en_US |
| dc.type | Thesis-Reproduction (electronic) | en_US |
| thesis.degree.grantor | University of Arizona | en_US |
| thesis.degree.level | masters | en_US |
| dc.identifier.proquest | 1346438 | en_US |
| thesis.degree.discipline | Graduate College | en_US |
| thesis.degree.name | M.S. | en_US |
| dc.identifier.bibrecord | .b27227728 | en_US |
| refterms.dateFOA | 2018-08-27T12:23:00Z | |
| html.description.abstract | Hardware description languages can be powerful tools in creating digital system designs. AHPL, A Hardware Programming Language, is a hardware description language that simplifies the task of designing a digital system. One of the major problems in using a hardware description language is interfacing with commercially available simulation and layout tools. Many commercial tools use the Electronic Design Interchange Format (EDIF) in order to communicate designs. This thesis describes the AHPL to EDIF Netlist Translator (AENT) program. By using AENT, a designer can write an AHPL description, verify the design with a function level simulator, and generate a CMOS standard cell layout using a commercial layout tool. A post layout gate level simulation can also be performed to verify timing constraints. Several layout examples are given in this thesis, and results are compared with the Berkeley Synthesis System. |
