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dc.contributor.advisorSchrimpf, Ronald D.en_US
dc.contributor.authorTodsen, James Lee, 1967-
dc.creatorTodsen, James Lee, 1967-en_US
dc.date.accessioned2013-04-03T13:16:11Z
dc.date.available2013-04-03T13:16:11Z
dc.date.issued1992en_US
dc.identifier.urihttp://hdl.handle.net/10150/278198
dc.description.abstractThe effects of high field stress on interface trap densities (Dit in MOS transistors are compared using three methods: charge-pumping, subthreshold swing and 1/f noise. The experimental MOS devices subjected to high field stress originated from two wafer lots processed with different concentrations of copper in the buffered oxide etchant. For the charge-pumping and subthreshold methods, no dependency is found on stress current polarity, wafer lot or transistor type (n- or p-channel). These two methods yield similar Dit values. For the 1/f noise method, no dependency is found on current polarity or wafer lot. However, the noise in the n-channel devices increases by several orders of magnitude as compared to the p-channel devices. A large discrepancy is found between Dit calculated from 1/f noise when compared to charge-pumping/subthreshold swing results for n-channel transistors. For p-channel transistors, the 1/f Dit results are in much better agreement with the results of the other two methods.
dc.language.isoen_USen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectEngineering, Electronics and Electrical.en_US
dc.titleComparison of interface trap measurements in high field stressed MOS transistorsen_US
dc.typetexten_US
dc.typeThesis-Reproduction (electronic)en_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.levelmastersen_US
dc.identifier.proquest1350390en_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.nameM.S.en_US
dc.identifier.bibrecord.b25124018en_US
refterms.dateFOA2018-06-24T18:35:42Z
html.description.abstractThe effects of high field stress on interface trap densities (Dit in MOS transistors are compared using three methods: charge-pumping, subthreshold swing and 1/f noise. The experimental MOS devices subjected to high field stress originated from two wafer lots processed with different concentrations of copper in the buffered oxide etchant. For the charge-pumping and subthreshold methods, no dependency is found on stress current polarity, wafer lot or transistor type (n- or p-channel). These two methods yield similar Dit values. For the 1/f noise method, no dependency is found on current polarity or wafer lot. However, the noise in the n-channel devices increases by several orders of magnitude as compared to the p-channel devices. A large discrepancy is found between Dit calculated from 1/f noise when compared to charge-pumping/subthreshold swing results for n-channel transistors. For p-channel transistors, the 1/f Dit results are in much better agreement with the results of the other two methods.


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