Simultaneous switching noise and its impact on CMOS digital systems
Publisher
The University of Arizona.Rights
Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.Abstract
Simultaneous switching noise was calculated for a number of CMOS drivers switching together. CMOS receiver noise immunity and the feed through of simultaneous switching noise from a D.C. "ON" driver were studied. The effects of skewing output driver switching on the simultaneous switching noise were explained. The performance trade-offs in using a damping resistor to minimize switching noise were analyzed. A distributed lumped equivalent model has been developed to model signal propagation over noisy reference planes, and thereby to accurately predict the overall noise levels in a system. The impact of package pin distribution on noise on the reference plane was analyzed.Type
textThesis-Reproduction (electronic)