Modeling the effect of copper contamination on junction diodes and MOS capacitors

Abstract

Copper in silicon is known to have detrimental effects on silicon devices. Therefore, understanding how copper affects device performance and how copper is distributed in semiconductor device regions are essential pieces of information that are required in order to eliminate copper contamination. This dissertation is primarily devoted to the study of the effects of copper contamination on junction leakage current of diodes and C-t responses of MOS Capacitors. Copper distributions in junction diodes and MOS capacitors were investigated by SIMS and TEM images. An increase of leakage current was observed with increasing copper concentration in heavily doped diode regions. The increase can be modeled by assuming the capture cross section as a function of copper gettered in the n+ or p+ region. Three different shapes of C-t responses were obtained from pulsed MOS capacitors contaminated with copper. S-PISCES simulations, in conjunction with the Zerbst technique, were used to examine the shapes of C-t responses. The three shapes of the C-t curves can be explained by introducing regions with different lifetimes in the simulations. The low minority carrier lifetime region near the Si/SiO2 interface correlates with copper SIMS profiles. The copper diffusion mechanism in n+ or p+ regions was also investigated.