A fractal compaction algorithm for efficient power estimation of CMOS designs

Abstract

In this dissertation, a vector compaction technique called the Fractal Compaction Algorithm is presented. The fractal compaction algorithm significantly reduces the time needed for estimating the power consumed in CMOS circuits. CMOS IC design requires accurate power estimation at every level in the design hierarchy. Power estimation methods that are currently available are either dynamic or static. Dynamic methods simulate the design using specific input vector sets and estimate the power consumed. Though accurate, dynamic methods require prohibitively long simulation time for large designs and large vector sets. Static power estimation methods, on the other hand, use analytical tools such as statistics and probability to estimate power. The static methods are usually fast but less accurate. To achieve both speed and accuracy, one approach would be to simulate with a compact vector set that has similar switching behavior as the original vector set. The algorithm presented in this work generates such a compact set using fractal concepts. It exploits the correlation present in the toggle distribution of a circuit's internal nodes for compacting the vector set. Instead of using correlation co-efficients, the fractal algorithm uses a simpler parameter, called the Hurst parameter to quantify correlation. The performance of fractal algorithm with combinational and sequential circuits showed very high compaction that can lead to a shorter design phase and quicker tape out. When compared to previously reported results, the fractal algorithm compacts much higher while keeping the estimation error low.