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dc.contributor.authorCarter, Ernest Aubert, 1942-
dc.creatorCarter, Ernest Aubert, 1942-en_US
dc.date.accessioned2013-05-02T09:55:49Z
dc.date.available2013-05-02T09:55:49Z
dc.date.issued1973en_US
dc.identifier.urihttp://hdl.handle.net/10150/288156
dc.language.isoen_USen_US
dc.publisherThe University of Arizona.en_US
dc.rightsCopyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.en_US
dc.subjectSCIRTSS (Computer program)en_US
dc.subjectDigital integrated circuits -- Testing.en_US
dc.subjectElectric fault location.en_US
dc.titleFAULT-TEST GENERATION FOR SEQUENTIAL CIRCUITS DESCRIBED IN AHPLen_US
dc.typetexten_US
dc.typeDissertation-Reproduction (electronic)en_US
dc.identifier.oclc29750794en_US
thesis.degree.grantorUniversity of Arizonaen_US
thesis.degree.leveldoctoralen_US
dc.identifier.proquest7411209en_US
thesis.degree.disciplineGraduate Collegeen_US
thesis.degree.disciplineElectrical Engineeringen_US
thesis.degree.namePh.D.en_US
dc.identifier.bibrecord.b31307036en_US
refterms.dateFOA2018-06-19T06:08:29Z


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