Capacitance calculations for three-dimensional VLSI interconnection geometries
| dc.contributor.advisor | Cangellaris, Andreas | en_US |
| dc.contributor.author | Omer, Ahmed Adan, 1964- | |
| dc.creator | Omer, Ahmed Adan, 1964- | en_US |
| dc.date.accessioned | 2013-05-16T09:23:19Z | |
| dc.date.available | 2013-05-16T09:23:19Z | |
| dc.date.issued | 1991 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10150/291396 | |
| dc.description.abstract | An integral equation formulation for the calculation of the capacitance of three-dimensional VLSI geometries is presented. A proper combination of 2D and 3D methods is used for efficient numerical computations. The method of moments is used for the solution of the integral equation. In addition, Green's functions that satisfy the boundary conditions at the dielectric interfaces are implemented in order to minimize the number of unknowns involved in the numerical solution. The mathematical formulation presented here and the associated computer program are appropriate for obtaining the capacitance matrix of complex three-dimensional multi-conductor configurations of the microstrip and the stripline type. Finally, numerical results for the per-unit-length capacitance and total capacitance of several interconnections are provided and compared with known results. Applications include the extraction of lumped capacitive elements used in the equivalent circuit representations of coupled conductor bends, vias and crossovers. In addition, calculations of per-unit-length capacitance of coupled flaring lines are performed. | |
| dc.language.iso | en_US | en_US |
| dc.publisher | The University of Arizona. | en_US |
| dc.rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | en_US |
| dc.subject | Engineering, Electronics and Electrical. | en_US |
| dc.subject | Engineering, Packaging. | en_US |
| dc.title | Capacitance calculations for three-dimensional VLSI interconnection geometries | en_US |
| dc.type | text | en_US |
| dc.type | Thesis-Reproduction (electronic) | en_US |
| thesis.degree.grantor | University of Arizona | en_US |
| thesis.degree.level | masters | en_US |
| dc.identifier.proquest | 1345437 | en_US |
| thesis.degree.discipline | Graduate College | en_US |
| thesis.degree.discipline | Electrical and Computer Engineering | en_US |
| thesis.degree.name | M.S. | en_US |
| dc.identifier.bibrecord | .b27031147 | en_US |
| refterms.dateFOA | 2018-08-29T23:48:41Z | |
| html.description.abstract | An integral equation formulation for the calculation of the capacitance of three-dimensional VLSI geometries is presented. A proper combination of 2D and 3D methods is used for efficient numerical computations. The method of moments is used for the solution of the integral equation. In addition, Green's functions that satisfy the boundary conditions at the dielectric interfaces are implemented in order to minimize the number of unknowns involved in the numerical solution. The mathematical formulation presented here and the associated computer program are appropriate for obtaining the capacitance matrix of complex three-dimensional multi-conductor configurations of the microstrip and the stripline type. Finally, numerical results for the per-unit-length capacitance and total capacitance of several interconnections are provided and compared with known results. Applications include the extraction of lumped capacitive elements used in the equivalent circuit representations of coupled conductor bends, vias and crossovers. In addition, calculations of per-unit-length capacitance of coupled flaring lines are performed. |
