A hardware compiler for VLSI synthesis applications

Abstract

Hardware description languages have been playing key roles in today's VLSI synthesis systems. AHPL is a hardware description language that can simplify the VLSI circuit design. An AHPL based VLSI synthesis system is introduced. HPCOM, a hardware compiler that translates an AHPL description into a logic network is a major part of the system. My research focuses on the development, use and interfacing between HPCOM and other synthesis tools. A finite state machine design that maps to the AHPL structure with minimal memory elements is developed. A minimization tool is incorporated into the HPCOM for Boolean logic minimization. Bus sub-type, an application-dependent parameter, and user defined logic are implemented. Memory contention problems are solved using overlay linking technique. Data structures of the HPCOM and methods for improving the usage of storage are discussed. A completed description of the data base produced by the compiler is provided.