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    A hardware compiler for VLSI synthesis applications

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    Author
    Chen, Jianxin, 1963-
    Issue Date
    1992
    Keywords
    Engineering, Electronics and Electrical.
    Advisor
    Hill, Fredrick J.
    
    Metadata
    Show full item record
    Publisher
    The University of Arizona.
    Rights
    Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author.
    Abstract
    Hardware description languages have been playing key roles in today's VLSI synthesis systems. AHPL is a hardware description language that can simplify the VLSI circuit design. An AHPL based VLSI synthesis system is introduced. HPCOM, a hardware compiler that translates an AHPL description into a logic network is a major part of the system. My research focuses on the development, use and interfacing between HPCOM and other synthesis tools. A finite state machine design that maps to the AHPL structure with minimal memory elements is developed. A minimization tool is incorporated into the HPCOM for Boolean logic minimization. Bus sub-type, an application-dependent parameter, and user defined logic are implemented. Memory contention problems are solved using overlay linking technique. Data structures of the HPCOM and methods for improving the usage of storage are discussed. A completed description of the data base produced by the compiler is provided.
    Type
    text
    Thesis-Reproduction (electronic)
    Degree Name
    M.S.
    Degree Level
    masters
    Degree Program
    Graduate College
    Electrical and Computer Engineering
    Degree Grantor
    University of Arizona
    Collections
    Master's Theses

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