A hardware compiler for VLSI synthesis applications
| dc.contributor.advisor | Hill, Fredrick J. | en_US |
| dc.contributor.author | Chen, Jianxin, 1963- | |
| dc.creator | Chen, Jianxin, 1963- | en_US |
| dc.date.accessioned | 2013-05-16T09:27:57Z | |
| dc.date.available | 2013-05-16T09:27:57Z | |
| dc.date.issued | 1992 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10150/291500 | |
| dc.description.abstract | Hardware description languages have been playing key roles in today's VLSI synthesis systems. AHPL is a hardware description language that can simplify the VLSI circuit design. An AHPL based VLSI synthesis system is introduced. HPCOM, a hardware compiler that translates an AHPL description into a logic network is a major part of the system. My research focuses on the development, use and interfacing between HPCOM and other synthesis tools. A finite state machine design that maps to the AHPL structure with minimal memory elements is developed. A minimization tool is incorporated into the HPCOM for Boolean logic minimization. Bus sub-type, an application-dependent parameter, and user defined logic are implemented. Memory contention problems are solved using overlay linking technique. Data structures of the HPCOM and methods for improving the usage of storage are discussed. A completed description of the data base produced by the compiler is provided. | |
| dc.language.iso | en_US | en_US |
| dc.publisher | The University of Arizona. | en_US |
| dc.rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | en_US |
| dc.subject | Engineering, Electronics and Electrical. | en_US |
| dc.title | A hardware compiler for VLSI synthesis applications | en_US |
| dc.type | text | en_US |
| dc.type | Thesis-Reproduction (electronic) | en_US |
| thesis.degree.grantor | University of Arizona | en_US |
| thesis.degree.level | masters | en_US |
| dc.identifier.proquest | 1350935 | en_US |
| thesis.degree.discipline | Graduate College | en_US |
| thesis.degree.discipline | Electrical and Computer Engineering | en_US |
| thesis.degree.name | M.S. | en_US |
| dc.identifier.bibrecord | .b26422700 | en_US |
| refterms.dateFOA | 2018-08-30T00:06:58Z | |
| html.description.abstract | Hardware description languages have been playing key roles in today's VLSI synthesis systems. AHPL is a hardware description language that can simplify the VLSI circuit design. An AHPL based VLSI synthesis system is introduced. HPCOM, a hardware compiler that translates an AHPL description into a logic network is a major part of the system. My research focuses on the development, use and interfacing between HPCOM and other synthesis tools. A finite state machine design that maps to the AHPL structure with minimal memory elements is developed. A minimization tool is incorporated into the HPCOM for Boolean logic minimization. Bus sub-type, an application-dependent parameter, and user defined logic are implemented. Memory contention problems are solved using overlay linking technique. Data structures of the HPCOM and methods for improving the usage of storage are discussed. A completed description of the data base produced by the compiler is provided. |
