Delay timing of Sea-of-Wire Array Logic

Abstract

Sea-of-Wire Array Logic has been developed to support a symbolic layout algorithm realization. A delay timing scheme is needed to direct the placement strategy of the layout. Both SPICE simulation and table lookup method are compared to verify the accuracy of delay estimation. Input waveform distortion is taken into account in the timing analysis, and correction factors are applied to increase the accuracy of delay estimation. A table lookup scheme has shown to be very accurate in comparison with SPICE value. A set of benchmark circuits have been applied to evaluate this table lookup scheme. The results obtained demonstrate a greater than 90% accuracy and five orders of magnitude increase in speed over SPICE simulation.