YOR: A yield optimizing routing algorithm by minimizing critical areas and vias

Abstract

Traditionally, the goal of channel routing algorithms is to route the nets with as few tracks as possible to minimize the chip area and achieve 100 percent connection. However, the manufacturing yield may not reach a satisfactory level if care is not taken to reduce the critical areas which are susceptible to defects. Our approach is to systematically eliminate critical areas by floating, burying, and bumping net segments as well as shifting vias. The yield optimizing routing (YOR) algorithm also minimizes the number of vias since vias in a chip increase the manufacturing complexity which again degrades the yield. The algorithm has been implemented and applied to benchmark routing layouts in the literature. The experimental results show that large reduction in the number of critical areas and significant improvement in yield are achieved, particularly for practical size channels such as the Deutsch's difficult problem.