Circuit emulation in a packet switching network

Abstract

When continuous bit streams are transmitted over packet switching networks, the 'packetized' version of the real time traffic in a periodic sequence is distorted due to random transmission delay and packet loss. The need to recover the original continuous bit stream requires an estimation of the original source clock. This clock regeneration is called Circuit Emulation. Using a single phase lock loop is insufficient since the packet arrival jitter (PAJ) is generally very large. A circuit emulation technique that has been recently proposed provides algorithms to estimate the frequency difference between the original transmitter clock and a local retiming clock. A tracking loop similar to a PLL has been designed in this thesis to regenerate the original transmitter clock from the frequency difference estimated. Performance and simulation are studied for the PLL. It is found that by an appropriate choice of the tracking loop parameters, the transmitter clock can be regenerated with minimal jitter and delay.