Passivation of III-V Semiconductor Surfaces

Abstract

Computer processor chips of the last generation are based on silicon, modified to achieve maximum charge mobility to enable fast switching speeds at low power. III-V semiconductors have charge mobilities that are much higher than that of silicon making them suitable candidates for boosting the performance of new electronic devices. However, III-V semiconductors oxidize rapidly in air after oxide etching and the poor quality of the resulting oxide limits device performance. Our goal is to design a liquid-phase process flow to etch the oxide and passivate the surface of III-V semiconductors and to understand the mechanism of layer formation.Self-assembled monolayers of 1-eicosanethiol (ET) dissolved in ethanol, IPA, chloroform, and toluene were deposited on clean InSb(100) surfaces. The InSb passivated surfaces were characterized after 0 to 60 min of exposure to air. Ellipsometry measurements showed a starting overlayer thickness (due to ET, oxides, or both) of about 20 Å in chloroform and from 32 to 35 Å in alcohols and toluene. Surface composition analysis of InSb with X-ray photoelectron spectroscopy after passivation with 0.1 mM ET in ethanol confirmed the presence of ET and showed that oxygen in the Auger region is below detection limits up to 3 min after the passivation. Our results show that a thiol layer on top of a non-oxidized or low-oxide semiconductor surface slows oxygen diffusion in comparison to a surface with no thiol present, making this a promising passivation method of III-V semiconductors.