Planar unijunction transistors for a neuristor realization
| dc.contributor.author | Wise, Joseph Brinton, 1941- | |
| dc.creator | Wise, Joseph Brinton, 1941- | en_US |
| dc.date.accessioned | 2014-06-03T15:23:11Z | |
| dc.date.available | 2014-06-03T15:23:11Z | |
| dc.date.issued | 1968 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10150/318686 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | The University of Arizona. | en_US |
| dc.rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | en_US |
| dc.subject | Transistor circuits. | en_US |
| dc.subject | Junction transistors. | en_US |
| dc.subject | Planar transistors. | en_US |
| dc.title | Planar unijunction transistors for a neuristor realization | en_US |
| dc.type | text | en_US |
| dc.type | Thesis-Reproduction (electronic) | en_US |
| dc.identifier.oclc | 29626651 | en_US |
| thesis.degree.grantor | University of Arizona | en_US |
| thesis.degree.level | masters | en_US |
| thesis.degree.discipline | Graduate College | en_US |
| thesis.degree.name | M.S. | en_US |
| dc.description.note | This item was digitized from a paper original. If you need higher-resolution images for any content in this item, please contact us at repository@u.library.arizona.edu. | |
| dc.identifier.bibrecord | .b31234045 | en_US |
| dc.identifier.callnumber | E9791 1968 22 | en_US |
| dc.description.admin-note | Original file replaced with corrected file June 2023. | |
| refterms.dateFOA | 2018-06-29T19:31:11Z |
