Optimum design and error analysis of digital integrators
| dc.contributor.author | Burt, Roger William, 1932- | |
| dc.creator | Burt, Roger William, 1932- | en_US |
| dc.date.accessioned | 2014-06-04T10:05:58Z | |
| dc.date.available | 2014-06-04T10:05:58Z | |
| dc.date.issued | 1963 | en_US |
| dc.identifier.uri | http://hdl.handle.net/10150/319721 | |
| dc.language.iso | en_US | en_US |
| dc.publisher | The University of Arizona. | en_US |
| dc.rights | Copyright © is held by the author. Digital access to this material is made possible by the University Libraries, University of Arizona. Further transmission, reproduction or presentation (such as public display or performance) of protected items is prohibited except with permission of the author. | en_US |
| dc.subject | Digital integrated circuits -- Design and construction. | en_US |
| dc.title | Optimum design and error analysis of digital integrators | en_US |
| dc.type | text | en_US |
| dc.type | Thesis-Reproduction (electronic) | en_US |
| dc.identifier.oclc | 28283029 | en_US |
| thesis.degree.grantor | University of Arizona | en_US |
| thesis.degree.level | masters | en_US |
| thesis.degree.discipline | Graduate College | en_US |
| thesis.degree.name | M.S. | en_US |
| dc.description.note | This item was digitized from a paper original. If you need higher-resolution images for any content in this item, please contact us at repository@u.library.arizona.edu. | |
| dc.identifier.bibrecord | .b28943223 | en_US |
| dc.identifier.callnumber | E9791 1963 41 | en_US |
| dc.description.admin-note | Original file replaced with corrected file June 2023. | |
| refterms.dateFOA | 2018-04-26T04:56:09Z |
