Design, Fabrication, and Characterization of High Density Silicon Photonic Components

Abstract

Our burgeoning appetite for data relentlessly demands exponential scaling of computing and communications resources leading to an overbearing and ever-present drive to improve efficiency while reducing on-chip area even as photonic components expand to fill application spaces no longer satisfied by their electronic counterparts. With a high index contrast, low optical loss, and compatibility with the CMOS fabrication infrastructure, silicon-on-insulator technology delivers a mechanism by which efficient, sub-micron waveguides can be fabricated while enabling monolithic integration of photonic components and their associated electronic infrastructure. The result is a solution leveraging the superior bandwidth of optical signaling on a platform capable of delivering the optical analogue to Moore's Law scaling of transistor density. Device size is expected to end Moore's Law scaling in photonics as Maxwell's equations limit the extent to which this parameter may be reduced. The focus of the work presented here surrounds photonic device miniaturization and the development of 3D optical interconnects as approaches to optimize performance in densely integrated optical interconnects. In this dissertation, several technological barriers inhibiting widespread adoption of photonics in data communications and telecommunications are explored. First, examination of loss and crosstalk performance in silicon nitride over SOI waveguide crossings yields insight into the feasibility of 3D optical interconnects with the first experimental analysis of such a structure presented herein. A novel measurement platform utilizing a modified racetrack resonator is then presented enabling extraction of insertion loss data for highly efficient structures while requiring minimal on-chip area. Finally, pioneering work in understanding the statistical nature of doublet formation in microphotonic resonators is delivered with the resulting impact on resonant device design detailed.